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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ADV7314 multiformat 216 mhz video encoder with six nsv 14-bit dacs features high definition input formats 8-/10-,16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel ycrcb compliant with: smpte 293m (525p) bta t-1004 edtv2 525p itu-r bt.1358 (625p/525p) itu-r bt.1362 (625p/525p) smpte 274m (1080i) at 30 hz and 25 hz smpte 296m (720p) rgb in 3 10-bit 4:4:4 input format hdtv rgb supported: rgb and rgbhv other high definition formats using async timing mode high definition output formats yprpb progressive scan (eia-770.1, eia-770.2) yprpb hdtv (eia 770.3) rgb, rgbhv cgms-a (720p/1080i) macrovision rev 1.1 (525p/625p) cgms-a (525p) standard definition input formats ccir-656 4:2:2 8-/10-/16-/20-bit parallel input standard definition output formats composite ntsc m/n composite pal m/n/b/d/g/h/i, pal-60 smpte 170m ntsc compatible composite video itu-r bt.470 pal compatible composite video s-video (y/c) euroscart rgb component yprpb (betacam, mii, smpte/ebu n10) macrovision rev 7.1.l1 cgms/wss closed captioning general features simultaneous sd and hd inputs and outputs oversampling up to 216 mhz programmable dac gain control sync outputs in all modes simplified functional block diagram clkin_a clkin_b hsync vsync blank y9?y0 c9?c0 s9?s0 timing generator pll o v e r s a m p l i n g i 2 c interface d e m u x standard definition control block color control brightness dnr gamma programmable filters sd test pattern high definition control block hd test pattern color control adaptive filter ctrl sharpness filter programmable rgb matrix 14-bit dac 14-bit dac 14-bit dac 14-bit dac 14-bit dac 14-bit dac ADV7314 general description the adv 7314 is a high speed, digital-to-analog encoder on a single monolithic chip. it includes six high speed nsv video d/a converters with ttl compatible inputs. the ADV7314 has separate 8-/10-/16-/20-bit input ports that accept data in high definition and/or standard definition video format. for all standards, external horizontal, vertical and blanking signals, or eav/sav timing codes control the inser- tion of appropriate synchronization signals into the digital data stream and therefore the output signal. on-board voltage reference six 14-bit nsv precision video dacs 2-wire serial i 2 c interface dual input/output supply 2.5 v/3.3 v operation analog and digital supply 2.5 v on-board pll 64-lead lqfp package lead (pb) free product applications high end dvd high end ps dvd recorders/players sd/prog scan/hdtv display devices sd/hdtv set top boxes professional video systems purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
rev. 0 e2e ADV7314 detailed features high definition programmable features (720p/1080i) 2 oversampling (148.5 mhz) internal test pattern generator (color hatch, black bar, flat field/frame) fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms-a (720p/1080i) programmable features (525p/625p) 8 oversampling (216 mhz output) internal test pattern generator (color hatch, black bar, flat frame) individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb matrix undershoot limiter macrovision rev 1.1 (525p/625p) cgms-a (525p) standard definition programmable features 16 oversampling (216 mhz) internal test pattern generator (color bars, black bar) controlled edge rates for sync, active video individual y and prpb output delay gamma correction digital noise reduction (dnr) multiple chroma and luma filters luma-ssafa filter with programmable gain/attenuation prpb ssaf separate pedestal control on component and composite/s-video outputs vcr ff/rw sync mode macrovision rev 7.1.l1 cgms/wss closed captioning standards directly supported frame rate clk input resolution (hz) (mhz) standard 720 480 29.97 27 itu-r bt.656 720 576 25 27 itu-r bt.656 720 483 59.94 27 smpte 293m 720 480 59.94 27 bta t-1004 720 576 50 27 itu-r bt.1362 1280 720 60 74.25 smpte 296m 1920 1080 30 74.25 smpte 274m 1920 1080 25 74.25 smpte 274m * other standards are supported in async timing mode. * smpte 274m-1998: system no.6 detailed functional block diagram s_hsync s_vsync s_blank clkin_a p _hsync p _vsync p _blank clkin_b hd pixel input sd pixel input deinter- leave y cb cr test pa ttern sharpness and adaptive filter cont luma and chroma filters f sc modula- tion rol y color cr color cb color 4:2:2 to 4:4:4 timing generator timing generator y cb cr test pa ttern dnr gamma color control sync insertion clock control and pll uv ssaf v u ps 8 hdtv 2 rgb matrix sd 16 cgms wss 2 over- sampling dac dac dac dac dac dac deinter- leave
rev. 0 ADV7314 ? table of contents programmable dac gain control . . . . . . . . . . 48 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 hd sharpness filter control and adaptive filter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 hd sharpness filter and adaptive filter application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 sd digital noise reduction . . . . . . . . . . . . . . . . 53 coring gain border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 coring gain data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 dnr threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 border area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 block size control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 dnr input select control . . . . . . . . . . . . . . . . . . . . . . . . 54 dnr mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 block offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 sd active video edge . . . . . . . . . . . . . . . . . . . . . . . . 55 sav/eav step edge control . . . . . . . . . . . . . . . . . . . . . . 55 board design and layout considerations . 56 dac termination and layout considerations . . . . . . . . 56 video output buffer and optional output filter . . . . . . . 56 pc board layout considerations . . . . . . . . . . 58 supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 digital signal interconnect . . . . . . . . . . . . . . . . . . . . . . . 58 analog signal interconnect . . . . . . . . . . . . . . . . . . . . . . . 58 appendix 1?opy generation management system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ps cgms data registers 2? . . . . . . . . . . . . . . . . . . . . . 60 sd cgms data registers 2? . . . . . . . . . . . . . . . . . . . . . 60 function of cgms bits . . . . . . . . . . . . . . . . . . . . . . . . . . 60 cgms functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 appendix 2?d wide screen signaling . . . . . . 62 appendix 3?d closed captioning . . . . . . . . . . 63 appendix 4?est patterns . . . . . . . . . . . . . . . . . . 64 appendix 5?d timing modes . . . . . . . . . . . . . . . 66 mode 0 (ccir-656)?lave option . . . . . . . . . . . . . . . . 66 mode 0 (ccir-656)?aster option . . . . . . . . . . . . . . . 67 mode 1?lave option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 mode 1?aster option . . . . . . . . . . . . . . . . . . . . . . . . . 69 mode 2?lave option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mode 2?aster option . . . . . . . . . . . . . . . . . . . . . . . . . 71 mode 3?aster/slave option . . . . . . . . . . . . . . . . . . . . . 72 appendix 6?d timing . . . . . . . . . . . . . . . . . . . . . . 73 appendix 7?ideo output levels . . . . . . . . . . . 74 hd yprpb output levels . . . . . . . . . . . . . . . . . . . . . . . . 74 rgb output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 yprpb output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 appendix 8?ideo standards . . . . . . . . . . . . . . . 80 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 82 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified functional block diagram . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 detailed functional block diagram . . . . . . . 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dynamic specifications . . . . . . . . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . 14 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pin function descriptions . . . . . . . . . . . . . . . . . 15 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 17 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 subaddress register (sr7?r0) . . . . . . . . . . . . . . . . . . . 18 input configuration . . . . . . . . . . . . . . . . . . . . . . . 31 standard definition only . . . . . . . . . . . . . . . . . . . . . . . . . 31 progressive scan only or hdtv only . . . . . . . . . . . . . . . 31 simultaneous standard definition and progressive scan or hdtv . . . . . . . . . . . . . . . . . . 32 progressive scan at 27 mhz (dual edge) or 54 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 output configuration . . . . . . . . . . . . . . . . . . . . . 34 timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 hd async timing mode . . . . . . . . . . . . . . . . . . . . . . . . . 35 hd timing reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 sd real-time control, subcarrier reset, and timing reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 sd vcr ff/rw sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 vertical blanking interval . . . . . . . . . . . . . . . . . . . . . . . . . 39 sd subcarrier frequency registers . . . . . . . . . . . . . . . . . 39 square pixel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 filter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 hd sinc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 sd internal filter response . . . . . . . . . . . . . . . . . . . . . . . 41 typical performance characteristics . . . . . . . . . . . . . . . . . . 42 color controls and rgb matrix . . . . . . . . . . . 46 hd/ps y level, cr level, cb level . . . . . . . . . . . . . . . . 46 hd rgb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 programming the rgb matrix . . . . . . . . . . . . . . . . . . . . . 46 sd luma and color control . . . . . . . . . . . . . . . . . . . . . . 46 sd hue adjust value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 sd brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 sd brightness detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
rev. 0 e4e ADV7314especifications (v aa = 2.375 ve2.625 v, v dd = 2.375 ve2.625 v; v dd_io = 2.375 ve3.6 v, v ref = 1.235 v, r set = 3040 , r load = 150 . all specifications t min to t max (0 c to 70 c), unless otherwise noted.) parameter min typ max unit test conditions static performance 1 resolution 14 bits integral nonlinearity 2.0 lsb differential nonlinearity 2 , +ve 1.0 lsb differential nonlinearity 2 , eve 3.0 lsb digital outputs output low voltage, v ol 0.4 [0.4] 3 vi sink = 3.2 ma output high voltage, v oh 2.4 [2.0] 3 vi source = 400 m a three-state leakage current 1.0 m av in = 0.4 v, 2.4 v three-state output capacitance 2 pf digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input leakage current 3 m av in = 2.4 v input capacitance, c in 2pf analog outputs full-scale output current 4.1 4.33 4.6 ma output current range 4.1 4.33 4.6 ma dac-to-dac matching 1.0 % output compliance range, v oc 0 1.0 1.4 v output capacitance, c out 7pf voltage reference internal reference range, v ref 1.15 1.235 1.3 v external reference range, v ref 1.15 1.235 1.3 v v ref current 4 10 m a power requirements normal power mode i dd 5 170 ma sd only [16 m a i aa 10 m a i dd_io 250 m a power supply rejection ratio 0.01 %/% notes 1 oversampling disabled. static dac performance will be improved with increased oversampling ratios. 2 dnl measures the deviation of the actual dac output voltage step from the ideal. for +ve dnl, the actual step value lies above the ideal step value; for eve dnl, the actual step value lies below the ideal step value. 3 value in brackets for v dd_io = 2.375 ve2.75 v. 4 external current required to overdrive internal v ref . 5 i dd , the circuit current, is the continuous current required to drive the digital core. 6 guaranteed maximum by characterization. 7 i aa is the total current required to supply all dacs including the v ref circuitry and the pll circuitry. 8 all dacs on. specifications subject to change without notice.
rev. 0 ADV7314 e5e dynamic specifications parameter min typ max unit test conditions progressive scan mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz snr 65.6 db luma ramp unweighted snr 72 db flat field full bandwidth hdtv mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz standard definition mode hue accuracy 0.44 %r eferenced to 40 ire chroma nonlinear phase e0.2 % chroma/luma gain inequality 97.5 % chroma/luma delay inequality 0 ns luminance nonlinearity 0.1 % chroma am noise 84 db chroma pm noise 75.3 db differential gain 0.09 % ntsc differential phase 0.12
rev. 0 e6e ADV7314 timing specifications (v aa = 2.375 ve2.625 v, v dd = 2.375 ve2.625 v; v dd_io = 2.375 ve3.6 v, v ref = 1.235 v, r set = 3040 , r load = 150 . all specifications t min to t max (0 c to 70 c), unless otherwise noted.) parameter min typ max unit conditions mpu port 1 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 0.6 m st he first clock is generated a fter this period setup time (start condition), t 4 0.6 m sr elevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 m s reset low time 100 ns analog outputs analog output delay 2 7ns output skew 1 ns clock control and pixel port 3 f clk 27 mhz progressive scan mode f clk 81 mhz hdtv mode/async mode clock high time t 9 40 % of one clk cycle clock low time t 10 40 % of one clk cycle data setup time t 11 1 2.0 ns data hold time t 12 1 2.0 ns sd output access time t 13 15 ns sd output hold time t 14 5.0 ns hd output access time t 13 14 ns hd output hold time t 14 5.0 ns pipeline delay 4 63 clk cycles sd [2 , 16 ] 76 clk cycles sd component mode [16 ] 35 clk cycles ps [1 ] 41 clk cycles ps [8 ] 36 clk cycles hd [2 , 1 ] notes 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: c [9:0]; y [9:0], s[9:0] control: p_hsync p_vsync p_blank s_hsync s_vsync s_blank s ps h h h s
rev. 0 ADV7314 e7e t 9 t 11 clkin_a c9?c0 t 10 t 12 p_hsync , p_vsyn c , p_blank cb0 cr0 cb2 cr2 cb4 cr4 y0 y1 y2 y3 y4 y5 y9?y0 t 14 control outputs t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time control inputs figure 1. hd only 4:2:2 input mode [input mode 010]; ps only 4:2:2 input mode [input mode 001] t 9 t 11 clkin_a c9?c0 t 10 t 12 p_hsync , p_vsync , p_blank cb0 cb1 cb2 cb3 cb4 cb5 y0 y1 y2 y3 y4 y5 y9?y0 t 14 control t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time s9?s0 cr0 cr1 cr2 cr3 cr5 outputs control inputs cr4 figure 2. hd only 4:4:4 input mode [input mode 010]; ps only 4:4:4 input mode [input mode 001]
rev. 0 e8e ADV7314 t 9 t 11 clkin_a c9?c0 t 10 t 12 p_hsync , p_vsync , control inputs g0 g1 g2 g3 g4 g5 b0 b1 b2 b3 b4 b5 r0 r1 r2 r3 r4 r5 y9?y0 t 14 control outputs t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time s9?s0 p_blank figure 3. hd rgb 4:4:4 input mode [input mode 010] control outputs t 9 t 11 t 10 t 12 t 11 t 12 t 13 t 14 clkin_b * * clkin_b must be used in this ps mode. y9?y t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time 0 p_hsync , p_vsync , p_blank control inputs cb0 y0 cr0 y1 crxxx yxxx figure 4. ps 4:2:2 1 hsync vsync
rev. 0 ADV7314 e9e t 9 t 11 t 10 t 12 cb0 y0 cr0 y1 crxxx yxxx t 14 t 13 clkin_a y9?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 = data hold time control outputs p_hsync , p_vsync , p_blank control inputs figure 5. ps 4:2:2 1 hsync vsync cn cnsenthssnye yy cchhte ccte tsette thte ycycy cntr tts s
rev. 0 e10e ADV7314 t 9 t 11 t 10 t 12 cb0 cr0 cb2 cr2 cb4 cr4 y0 y1 y2 y3 y4 y5 cb0 y0 cr0 y1 cb1 y2 t 9 t 10 t 11 t 12 hd input sd input s9?s0 clkin_a clkin_b y9?y0 c9?c0 p_hsync , p_vsync , p_blank control inputs s_hsync , s_vsync , s_blank control inputs figure 8. hd 4:2:2 and sd (10-bit) simultaneous input mode [input mode 101]; sd oversampled [input mode 110] hd oversampled t 9 t 11 t 10 t 12 cb0 cr0 cb2 cr2 cb4 cr4 y0 y1 y2 y3 y4 y5 cb0 y0 cr0 y1 cb1 y2 t 9 t 10 t 11 t 12 ps input sd input s9?s0 clkin_a clkin_b y9?y0 c9?c0 p_hsync , p_vsync , p_blank control inputs s_hsync , s_vsync , s_blank control inputs figure 9. ps (4:2:2) and sd (10-bit) simultaneous input mode [input mode 011]
rev. 0 ADV7314 e11e s9?s0 cb0 y0 cr0 y1 cb1 y2 clkin_a t 9 t 10 t 11 t 12 sd input t 9 t 11 clkin_b y9?y0 t 10 t 12 t 11 t 12 ps input crxxx yxxx cb0 y0 cr0 y1 p_hsync , p_vsync , p_blank control inputs s_hsync , s_vsync , s_blank control inputs figure 10. ps (10-bit) and sd (10-bit) simultaneous input mode [input mode 100] t 9 t 11 clkin_a s9?s0/y9?y0 * t 10 t 12 cb0 cr0 cb2 cr2 cb4 cr4 t 14 control outputs t 13 * selected by address 0x01 bit 7 in master/slave mode in slave mode s_hsync , s_vsync , s_blank control inputs figure 11. 10-/8-bit sd only pixel input mode [input mode 000]
rev. 0 e12e ADV7314 t 9 t 11 clkin_a c9?c0 t 10 t 12 cb0 cr0 cb2 cr2 t 14 t 13 * selected by address 0x01 bit 7 in master/slave mode in slave mode s9?s0/y9?y0 * y0 y2 y3 y1 control outputs s_hsync , s_vsync , s_blank control inputs figure 12. 20-/16-bit sd only pixel input mode [input mode 000] p _hsync p_vsync p_blank y9?y0 y0 y1 y2 y3 c9?c0 cb0 cr0 cr1 cb1 b a a = 16 clk cycles for 525p a = 12 clk cycles for 626p a = 44 clk cycles for 1080i @ 30hz, 25hz a = 70 clk cycles for 720p as recommended by standard b (min) = 122 clk cycles for 525p b (min) = 132 clk cycles for 625p b (min) = 236 clk cycles for 1080i @ 30hz, 25hz b (min) = 300 clk cycles for 720p figure 13. hd 4:2:2 input timing diagram
rev. 0 ADV7314 e13e p _hsync p_vsync p_blank y9?y0 cb y cr y b a a = 32 clk cycles for 525p a = 24 clk cycles for 625p as recommended by standard b(min) = 244 clk cycles for 525p b(min) = 264 clk cycles for 625p figure 14. ps 4:2:2 1
rev. 0 e14e ADV7314 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7314 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * v aa to agnd . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to e0.3 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to e0.3 v v dd_io to io_gnd . . . . . . . . . . . . e0.3 v to v dd_io to +0.3 v ambient operating temperature (t a ) . . . . . . . . . 0 5
rev. 0 ADV7314 e15e pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin 1 identifier top view (not to scale) v dd_io 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 y0 y1 y2 y3 y4 y5 y6 y7 v dd dgnd y8 y9 c0 c1 c2 s_blan k r set1 v ref comp1 dac a dac b dac c v aa a gnd dac d dac e dac f comp2 r set2 ext_lf reset c3 c4 i 2 c alsb sda sclk p_hsync p_vsync p_blank c5 c6 c7 c8 c9 rt c_scr_tr clkin_a gnd_io clkn_b s9 s8 s7 s6 s5 dgnd v dd s4 s3 s2 s1 s0 s_hsyn c s_vsync ADV7314 lqfp pin function descriptions pin no. mnemonic input/output function 11, 57 dgnd g digital ground. 40 agnd g analog ground. 32 clkin_a i pixel clock input for hd (74.25 mhz only, ps only (27 mhz), sd only (27 mhz). 63 clkin_b i pixel clock input. requires a 27 mhz reference clock for progressive scan mode or a 74.25 mhz (74.1758 mhz) reference clock in hdtv mode. this clock is only used in dual modes. 36, 45 comp2, comp1 o compensation pin for dacs. connect 0.1 m f capacitor from comp pin to v aa . 44 dac a o cvbs/green/y/y analog output. 43 dac b o chroma/blue/u/pb analog output. 42 dac c o luma/red/v/pr analog output. 39 dac d o in sd only mode: cvbs/green/y analog output. in hd only mode and simultaneous hd/sd mode: y/green [hd] analog output. 38 dac e o in sd only mode: luma/blue/u analog output. in hd only mode and simultaneous hd/sd mode: pr/red analog output. 37 dac f o in sd only mode: chroma/red/v analog output. in hd only mode and simultaneous hd/sd mode: pb/blue [hd] analog output. 23 p_hsync v h s c s h s sh h p_vsync v v s c s h s sh h p_blank v b c s h s sh h s_blank v b c s s
rev. 0 e16e ADV7314 pin no. mnemonic input/output function 50 s_hsync v h s c s s s_vsync v v s c s s yy s p shtv p y t lsb p y lsb y cc p shtv p cb t lsb p c lsb c ss s p shtv p c rv lsb p s lsb s reset t av reset r set r set a w resistor must be connected from this pin to agnd and is used to control the amplitudes of the dac outputs. 22 sclk i i 2 c port serial interface clock input. 21 sda i/o i 2 c port serial data input/output. 20 alsb i ttl address input. this signal sets up the lsb of the i 2 c address. when this pin is tied low, the i 2 c filter is activated, reducing noise on the i 2 c interface. 1v dd_io pp ower supply for digital inputs and outputs. 10, 56 v dd pd igital power supply. 41 v aa pa nalog power supply. 46 v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235 v). 34 ext_lf i external loop filter for the internal pll. 31 rtc_scr_tr i multifunctional input. real-time control (rtc) input, timing reset input, subcarrier reset input. 19 i 2 ci this input pin must be tied high (v dd_io ) for the ADV7314 to interface over the i 2 c port. 64 gnd_io digital input/output ground. terminology sd standard definition video, conforming to itu-r bt.601/656. hd high definition video, such as progressive scan or hdtv. ps progressive scan video, conforming to smpte 293m, itu-r bt.1358, bta t-1004 edtv2, bta 1362 hdtv high definition television video, conforming to smpte 274m or smpte 296m. ycrcb sd, hd, or ps component digital video. yprpb hd, sd, or ps component analog video.
rev. 0 ADV7314 e17e mpu port description the ADV7314 supports a 2-wire serial (i 2 c compatible) micro- processor bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (scl), carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7314 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 17. the lsb sets either a read or write operation. logic 1 corresponds to a read operation, while logic 0 corresponds to a write opera- tion. a1 is set by setting the alsb pin of the ADV7314 to logic 0 or logic 1. when alsb is set to 1, there is greater input bandwidth on the i 2 c lines, which allows high speed data transfers on this bus. when alsb is set to 0, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recommended for noisy systems. 1 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read figure 17. ADV7314 slave address = d4h to control the various devices on the bus, the following protocol must be followed. first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda, while scl remains high. this indicates that an address/ data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w t sb lsb t t a t sa scl t r w a l lsb a l lsb t av t sa r w t a t s scl av t a sa av
rev. 0 e18e ADV7314 before writing to the subcarrier frequency registers, the ADV7314 m ust have b een reset at least once since power-up. the four subcarrier frequency registers must be updated start- ing with subcarrier frequency register 0 through subcarrier frequency register 3. the subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7314. figure 18 illustrates an example of the data transfer for a write sequence and the start and stop conditions. figure 19 shows bus write and read sequences. register access the mpu can write to or read from all of the registers of the ADV7314 except the subaddress registers, which are write-only registers. the subaddress register determines which register the sdata sclock start adrr r/ w ack subaddress ack data ack stop 1?7 8 9 s 1?7 8 9 1?7 89 p figure 18. bus data transfer write sequence read sequence s slave addr a(s) sub addr a(s) data a(s) data a(s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data data a(m) a (m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 figure 19. write and read sequence next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address, which increments to the next address until a stop command on the bus is performed. register programming the following section describes the functionality of each register. all registers can be read from as well as written to unless other- wise stated. subaddress register (sr7esr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write opera- tion is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place.
rev. 0 ADV7314 e19e sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting register reset value (shaded) 0s leep mode off fch 1s leep mode on 0 pll on 1 pll off 0 dac f off 1 dac f on 0 dac e off 1 dac e on 0 dac d off 1 dac d on 0 dac d off 1 dac c on 0 dac b off 1 dac b on 0 dac a off 1 dac a on 0dis abled 1 enabled 0 cb clocked on rising edge 1y clocked on rising edge reserved 0 38h 0 1 must be set if the phase delay between the two input clocks is <9.25 ns or >27.75 ns. only if two input clocks are used 00 0 sd input only 00 1 ps input only 01 0 hdtv input only 011 sd and ps [20-bit] 100 sd and ps [10-bit] 10 1 sd and hdtv [sd oversampled 11 0 sd and hdtv [hdtv oversampled] 111 ps only [at 54 mhz] 0 10-bit data on s bus 1 10-bit data on y bus sd only. 10-bit/ 20-bit input mode pll and oversampling control. this control allows the internal pll cct to be powered down and the oversampling to be switched off. sleep mode. with this control enabled, the current consumption is reduced to
rev. 0 e20e ADV7314 sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 02h mode register 0 reserved 00 zero must be written to these bits 20h test pattern black bar 0 disabled 1 enabled rgb matrix 0 disable programmable rgb matrix 1 enable programmable rgb matrix sync on rgb 1 0 no sync 1 sync on all rgb outputs rgb/yuv output 0 rgb component outputs 1 yuv component outputs sd sync 0 no sync output 1 output sd syncs on s_hsync s_vsync s_blank h s n s h p_hsync p_vsync p_blank rb lsb y rb lsb rv lsb b lsb v lsb rb b y e rb b e rb b v rb b b rb b rv c a ac abc l p ac v n ac v b ac e l p ac v n ac v c n n e r r b a p ac c
rev. 0 ADV7314 e21e sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 10h hd output standard 0 0 eia770.2 output 00h 01 ei a770.1 output 10 output levels for full input ran g e 11 reserved hd input control signals 0 0 hsync vsync blank eavsav a r h h h blank p blank blank h h p v p p r h t p e h h h t p h h h vb e h l re re re h s e h r h r
rev. 0 e22e ADV7314 notes 1 when set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. wh en set to 1 , the field/line counters are free running and wrap around when external sync signals indicate so. 2 adaptive filter mode is not available in ps only @ 54 mhz input mode. sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 12h 0000 clk cycle 00h 0011 clk cycle 0102 clk cycle 0113 clk cycle 1004 clk cycle 00 0 0 clk cycle 00 1 1 clk cycle 01 0 2 clk cycle 01 1 3 clk cycle 10 0 4 clk cycle hd cgms 0 disabled 1 enabled hd cgms crc 0 disabled 1 enabled 13h hd cr/cb sequence 0 cb after falling edge of hsync c c hsync r e r h c ssa e h c e h r h t r a h r h h r vsync l r h rb e h s pp e h c ac s ac e p ac p ac e p ac p h c ab c a c b h c e e h a a b h a e e h b h r h r h r h vsync s ac e h h r e hsync h y r e hsync
rev. 0 ADV7314 e23e sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 16h hd y level 1 xxxxx xx x y color value a0h 17h hd cr level 1 xxxxx xx x cr color value 80h 18h hd cb level 1 xxxxx xx x cb color value 80h 19h reserved 00h 1ah reserved 00h 1bh reserved 00h 1ch reserved 00h 1dh reserved 00h 1eh reserved 00h 1fh reserved 00h 0 disabled 1 enabled 0m ode a 1m ode b 0 disabled 1 enabled 20h 00 00 gain a = 0 00h 00 01 gain a = +1 .. .. .. .. 01 11 gain a = +7 100 0 gain a = e8 .. .. .. .. 111 1 gain a = e1 0000 gain b = 0 0001 gain b = +1 .. .. .. .. . 0111 gain b = +7 1000 gain b = e8 .. .. .. .. .. 1111 gain b = e1 21h 2 hd cgm s hd cgms data bits 0000c19c18c17c16cgms 19e16 00h 22h hd cgm s hd cgms data bits c15 c14 c13 c12 c11 c10 c9 c8 cgms 15e8 00h 23h hd cgm s hd cgms data bits c7 c6 c5 c4 c3 c2 c1 c0 cgms 7e0 00h 24h hd gamma a 1 hd gamma curve a data points xxxxx xx x a0 00h 25h hd ga mma a hd gamma curve a data points xxxxx xx x a1 00h 26h hd ga mma a hd gamma curve a data points xxxxx xx x a2 00h 27h hd ga mma a hd gamma curve a data points xxxxx xx x a3 00h 28h hd ga mma a hd gamma curve a data points xxxxx xx x a4 00h 29h hd ga mma a hd gamma curve a data points xxxxx xx x a5 00h 2ah hd ga mma a hd gamma curve a data points xxxxx xx x a6 00h 2bh hd ga mma a hd gamma curve a data points xxxxx xx x a7 00h 2ch hd ga mma a hd gamma curve a data points xxxxx xx x a8 00h 2dh hd gamma a hd gamma curve a data points xxxxx xx x a9 00h 2eh hd gamma b hd gamma curve b data points xxxxx xx x b0 00h 2fh hd gamma b hd gamma curve b data points xxxxx xx x b1 00h 30h hd gamma b hd gamma curve b data points xxxxx xx x b2 00h 31h hd gamma b hd gamma curve b data points xxxxx xx x b3 00h 32h hd gamma b hd gamma curve b data points xxxxx xx x b4 00h 33h hd gamma b hd gamma curve b data points xxxxx xx x b5 00h 34h hd gamma b hd gamma curve b data points xxxxx xx x b6 00h 35h hd gamma b hd gamma curve b data points xxxxx xx x b7 00h 36h hd gamma b hd gamma curve b data points xxxxx xx x b8 00h 37h 2 hd gamma b hd gamma curve b data points xxxxx xx x b9 00h hd sharpness filter gain value a hd sharpness filter gain value b 15h hd mode register 6 hd gamma curve enable hd adaptive filter mode hd adaptive filter enable hd sharpness filter gain notes 1 used for internal test pattern only. 2 programmable gamma correction is not available in ps only mode @ 54 mhz operation.
rev. 0 e24e ADV7314 sr7esr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting value 38h hd adaptive filter 0 0 0 0 gain a = 0 00h gain 1 00 0 1 gain a = +1 .. .. .. .. 01 1 1 gain a = +7 10 0 0 gain a = e8 .. .. .. .. 11 1 1 gain a = e1 0000 gain b = 0 0001 gain b = +1 .. .. .. .. . 0111 gain b = +7 1000 gain b = e8 .. .. .. .. .. 1111 gain b = e1 39h 00 0 0 gain a = 0 00h 00 0 1 gain a = +1 .. .. .. .. 01 1 1 gain a = +7 10 0 0 gain a = e8 .. .. .. .. 11 1 1 gain a = e1 0000 gain b = 0 0001 gain b = +1 .. .. .. .. . 0111 gain b = +7 1000 gain b = e8 .. .. .. .. .. 1111 gain b = e1 3ah 00 0 0 gain a = 0 00h 00 0 1 gain a = +1 .. .. .. .. 01 1 1 gain a = +7 10 0 0 gain a = e8 .. .. .. .. 11 1 1 gain a = e1 0000 gain b = 0 0001 gain b = +1 .. .. .. .. . 0111 gain b = +7 1000 gain b = e8 .. .. .. .. .. 1111 gain b = e1 hd adaptive filter threshold a xxxxxx x x thr eshold a 00h hd adaptive filter threshold b xxxxxx x x thr eshold b 00h hd adaptive filter threshold c xxxxxx x x thr eshold c 00h hd adaptive filter gain 1 value a hd adaptive filter gain 1 value b hd adaptive filter threshold c value hd adaptive filter gain 3 value b hd adaptive filter threshold b value hd adaptive filter threshold a value 3bh 3ch 3dh hd adaptive filter gain 3 hd adaptive filter gain 2 value a hd adaptive filter gain 2 value b hd adaptive filter gain 2 hd adaptive filter gain 3 value a
rev. 0 ADV7314 e25e sr7e sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 3eh reserved 00h 3fh reserved 00h 40h sd mode register 0 sd standard 0 0 ntsc 00h 01 pal b, d, g, h, i 10 pal m 11 pal n sd luma filter 0 0 0 lpf ntsc 00 1 lpf pal 01 0 notch ntsc 01 1 notch pal 10 0 ssaf luma 10 1 luma cif 11 0 luma qcif 11 1 reserved sd chroma filter 0 0 0 1.3 mhz 001 0.65 mhz 010 1.0 mhz 011 2.0 mhz 100 reserved 101 chroma cif 110 chroma qcif 111 3.0 mhz 41h reserved 00h 42h sd mode register 1 sd uv ssaf 0 disabled 08h 1 enabled sd dac output 1 0 1 sd dac output 2 0 1 sd pedestal 0 disabled 1 enabled sd square pixel 0 disabled 1 enabled sd vcr ff/rw sync 0 disabled 1 enabled sd pixel data valid 0 disabled 1 enabled 0 disabled 1 enabled 43h sd mode register 2 sd pedestal yprpb output 0 no pedestal on yuv 00h 1 7.5 ire pedestal on yuv sd output levels y 0 y = 700/300 mv 1 y = 714/286 mv sd output levels prpb 0 0 700 mv p-p[pal]; 1000 mv p-p[ntsc] 01 700 mv p-p 10 1000 mv p-p 11 648 mv p-p sd vbi open 0 disabled 1 enabled sd cc field control 0 0 cc disabled 01 cc on odd field only 10 cc on even field only 11 cc on both fields reserved 0 reserved refer to output configuration section refer to output configuration section sd sav/eav step edge control
rev. 0 e26e ADV7314 sr7e sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 44h sd mode register sd vs ync e3h 0 disabled 00h 1 vsync al vsync nsc scsc s c sav l nscal sc c c sb scb sacs s ss sys sha sb s l ss a s sb s sn sc sc ca cb s s l sbb sc acblaccc acbcaccl scc
rev. 0 ADV7314 e27e sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4b it 3 bit 2 bit 1 bit 0 register setting reset value 4ah sd timing register 0 sd slave/master mode 0 slave mode 08h 1m aster mode sd timing mode 0 0 mode 0 01 mode 1 10 mode 2 11 mode 3 sd blank sl n slv s a s b s s hsyn c s hsync vsync hsync vsync vsync hsync a line 313 line 314 line 1 t b h sync vsync t a t c figure 20. timing register 1 in pal mode
rev. 0 e28e ADV7314 sr7e sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 59h sd cgms/wss 0 sd cgms data 19 18 17 16 c gms data bits c19ec16 00h sd cgms crc 0 disabled 1 enabled sd cgms on odd 0 disabled 1 enabled sd cgms on even 0 disabled 1 enabled sd wss 0 disabled 1 enabled 5ah sd cgms/wss 1 sd cgms/wss data 13 12 11 10 9 8 cgms data bits c13ec8 or wss data bits c13ec8 00h 15 14 cgms data bits c15ec14 00h 5bh sd cgms/wss 2 sd cgms/wss data 7 6 5 4 3 2 1 0 c gms/wss data bits c7ec0 00h 5ch sd lsb register sd lsb for y scale x x sd y scale bit 1e0 sd lsb for u scale x x sd u scale bit 1e0 sd lsb for v scale x x sd v scale bit 1e0 sd lsb for f sc phase x x subcarrier phase bits 1e0 5dh sd y scale sd y scale value x x x x x x x x sd y scale bit 7e2 00h 5eh sd v scale sd v scale value x x x x x x x x sd v scale bit 7e2 00h 5fh sd u scale sd u scale value x x x x x x x x sd u scale bit 7e2 00h 60h sd hue register sd hue adjust value x x x x xxx x sd hue adjust bit 7e0 00h 61h sd brightness value x x x x x x x sd brightness bit 6e0 00h sd blank wss data 0 disabled line 23 1 enabled 62h sd luma ssaf 0 0 0 0 0 0 0 0 e4 db 00h 0000011 00 db 0000110 0 +4 db 63h sd dnr 0 coring gain border 0 0 0 0 no gain 00h 000 1 +1/16 [e1/8] 001 0 +2/16 [e2/8] 001 1 +3/16 [e3/8] 010 0 +4/16 [e4/8] 010 1 +5/16 [e5/8] 011 0 +6/16 [e6/8] 011 1 +7/16 [e7/8] 100 0 +8/16 [e1] coring gain data 0 0 0 0 no gain 00 01 +1/16 [e1/8] 00 10 +2/16 [e2/8] 00 11 +3/16 [e3/8] 01 00 +4/16 [e4/8] 01 01 +5/16 [e5/8] 01 10 +6/16 [e6/8] 01 11 +7/16 [e7/8] 10 00 +8/16 [e1] 64h sd dnr 1 dnr threshold 0 0 0 0 0 0 0 00h 00 000 11 11 111 062 11 111 163 border area 0 2 pixels 14 pixels block size control 08 pixels 116 pixels in dnr mode the values in brackets apply sd brightness/ wss sd luma ssaf gain/attenuation
rev. 0 ADV7314 e29e sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 65h sd dnr 2 dnr input select 0 01 filter a 00h 0 10 filter b 0 11 filter c 1 0 0 filter d dnr mode 0 dnr mode 1 dnr sharpness mode dnr block offset 0 0 0 0 0 pixel offset 000 11 pixel offset 111 0 14 pixel offset 111 1 15 pixel offset 66h sd ga mma as d gamma curve a data points x x x xxxx x a0 00h 67h sd ga mma as d gamma curve a data points x x x xxxx x a1 00h 68h sd ga mma as d gamma curve a data points x x x xxxx x a2 00h 69h sd ga mma as d gamma curve a data points x x x xxxx x a3 00h 6ah sd ga mma as d gamma curve a data points x x x xxxx x a4 00h 6bh sd ga mma as d gamma curve a data points x x x xxxx x a5 00h 6c hs d ga mma as d gamma curve a data points x x x xxxx x a6 00h 6dh sd gamma a sd gamma curve a data points x x x xxxx x a7 00h 6eh sd ga mma as d gamma curve a data points x x x xxxx x a8 00h 6f hs d ga mma as d gamma curve a data points x x x xxxx x a9 00h 70h sd gamma b sd gamma curve b data points x x x xxxx x b0 00h 71h sd gamma b sd gamma curve b data points x x x xxxx x b1 00h 72h sd gamma b sd gamma curve b data points x x x xxxx x b2 00h 73h sd gamma b sd gamma curve b data points x x x xxxx x b3 00h 74h sd gamma b sd gamma curve b data points x x x xxxx x b4 00h 75h sd gamma b sd gamma curve b data points x x x xxxx x b5 00h 76h sd gamma b sd gamma curve b data points x x x xxxx x b6 00h 77h sd gamma b sd gamma curve b data points x x x xxxx x b7 00h 78h sd gamma b sd gamma curve b data points x x x xxxx x b8 00h 79h sd gamma b sd gamma curve b data points x x x xxxx x b9 00h 7ah sd brightness detect sd brightness value x x x xxx xxr ead only 7bh field count register field count x x x read only reserved 0 0 m ust be written to this reserved 0 0 m ust be written to this reserved 0 0 m ust be written to this revision code x x read only 7c h 10-bit input 0 0 0 000 10 must write this for 10 bit data input (sd, ps, hd) 00h
rev. 0 e30e ADV7314 sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 7dh reserved 7e h reserved 7f h reserved 80h macrovision mv control bits x x xxxxxx 00h 81h macrovision mv control bits x x xxxxxx 00h 82h macrovision mv control bits x x xxxxxx 00h 83h macrovision mv control bits x x xxxxxx 00h 84h macrovision mv control bits x x xxxxxx 00h 85h macrovision mv control bits x x xxxxxx 00h 86h macrovision mv control bits x x xxxxxx 00h 87h macrovision mv control bits x x xxxxxx 00h 88h macrovision mv control bits x x xxxxxx 00h 89h macrovision mv control bits x x xxxxxx 00h 8ah macrovision mv control bits x x xxxxxx 00h 8bh macrovision mv control bits x x xxxxxx 00h 8c hm acrovision mv control bits x x xxxxxx 00h 8dh macrovision mv control bits x x xxxxxx 00h 8e hm acrovision mv control bits x x xxxxxx 00h 8f hm acrovision mv control bits x x xxxxxx 00h 90h macrovision mv control bits x x xxxxxx 00h 91h macrovision mv control bit x 00h 00 00000 0 must be written to bits
rev. 0 ADV7314 e31e input configuration when 10-bit input data is applied, the following bits must be set to 1: address 0x7c, bit 1 (global 10-bit enable) address 0x13, bit 2 (hd 10-bit enable) address 0x48, bit 4 (sd 10-bit enable) note that the ADV7314 defaults to simultaneous standard definition and progressive scan on power-up. address[01h]: input mode = 011. standard definition only address [01h] input mode = 000 the 8-bit/10-bit multiplexed input data is input on pins s9es0 (or y9ey0, depending on register address 0x01, bit7), with s0 being the lsb in 10-bit input mode. input standards supported are itu-r bt.601/656. in 16-bit input mode, the y pixel data is input on pins s9es2, and crcb data is input on pins c9ec2. the 27 mhz clock input must be input on the clkin_a pin. input sync signals are optional and are input on the s_vsync s_ hsync s_blank mpeg2 decoder s_vsync s_hsync s_blank clkin_a s[9:0] or y[9:0] * 27mhz 3 10 ycrcb ADV7314 * selected by address 0x01 bit 7 figure 21 . sd only input mode progressive scan only or hdtv only address [01h] input mode 001 or 010, respectively ycrcb progressive scan, hdtv, or any other hd ycrcb data can be input in 4:2:2 or 4:4:4. in 4:2:2 input mode, the y data is input on pins y9ey0 and the crcb data on pins c9ec0. in 4:4:4 input mode, y data is input on pins y9ey0, cb data on pins c9ec0, and cr data on pins s9es0. if the ycrcb data does not conform to smpte 293m (525p), itu-r bt.1358m (625p), smpte 274m (1080i), smpte 296m (720p), or bta t-1004/1362, the async timing mode must be used. rgb data can be input in 4:4:4 format in ps input mode only or in hdtv input mode only when hd rgb input is enabled. g data is input on pins y9ey0, r data on s9es0, and b data on c9ec0. the clock signal must be input on the clkin_a pin. mpeg2 decoder p_vsync p_hsync p_blank clkin_a c[9:0] 10 cb s[9:0] y[9:0] interlaced to progressive ycrcb 10 cr 10 y 3 27mhz ADV7314 figure 22. progressive scan input mode
rev. 0 e32e ADV7314 simultaneous standard definition and progressive scan or hdtv address [01h]: input mode 011(sd 40-bit, ps 20-bit) or 101 (sh and hd, sd oversampled), 110 (sd and hd, hd oversampled) ycrcb ps, hdtv, or any other hd data must be input in 4:2:2 format. in 4:2:2 input mode, the hd y data is input on pins y9ey0 and the hd crcb data on c9ec0. if ps 4:2:2 data is interleaved onto a single 10-bit bus, y9ey0 are used for the input port. the input data is to be input at 27 mhz with the data clocked on the rising and falling edge of the input clock. the input mode register at address 01h is set accordingly. if the ycrcb data does not conform to smpte 293m (525p), itu-r bt.1358m (625p), smpte 274m (1080i), smpte 296m (720p), or bta t-1004, the async timing mode must be used. the 8-bit or 10-bit standard definition data must be compliant to itu-r bt.601/656 in 4:2:2 format. standard definition data is input on pins s9es0, with s0 being the lsb. using 8-bit input format, the data is input on pins s9es2. the clock input for sd must be input on clkin_a, and the clock input for hd must be input on clkin_b. synchronization signals are optional. sd syncs are input on pins s_vsync s_ hsync s_blank h p p_vsync p_ hsync p_blank s_vsync s_hsync s_blank clkin_a p_vsync p_hsync p_blank clkin_b mpeg2 decoder 3 27mhz 10 ycrcb interlaced to progressive 10 crcb 10 y 3 27mhz s[9:0] c[9:0] y[9:0] ADV7314 figure 23. simultaneous ps and sd input s_vsync s_hsync s_blank clkin_a p_vsync p_hsync p_blank clkin_b sdtv decoder 3 27mhz 10 ycrc b hdtv decoder 10 crcb 10 y 3 74.25mhz 1080 i 720 p s[9:0] c[9:0] y[9:0] ADV7314 figure 24. simultaneous hd and sd input if in simultaneous sd/hd input mode, the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the clock align bit [address 01h, bit 3] must be set accordingly. if the application uses the same clock source for both sd and ps, the clock align bit must be set since the phase difference between both inputs is less than 9.25 ns. t delay 9.25ns or t delay 27.75ns clkin_a clkin_b figure 25. clock phase with two input clocks progressive scan at 27 mhz (dual edge) or 54 mhz address [01h]: input mode 100 or 111, respectively ycrcb progressive scan data can be input at 27 mhz or 54 mhz. the input data is interleaved onto a single 8-/10-bit bus and is input on pins y9ey0. when a 27 mhz clock is supplied, the data is clocked in on the rising and falling edge of the input clock and clock edge [address 01h, bit 1] must be set accordingly. the following figures show the possible conditions. (a) cb data on the rising edge and (b) y data on the rising edge. 3ff 00 00 xy y0 y1 cr0 clkin_b y9?y0 cb0 figure 26a. clock edge address 01h, bit 1 should be set to 0 3ff 00 00 xy cb0 cr0 y1 clkin_b y9?y0 y0 figure 26b. clock edge address 01h, bit 1 should be set to 1 with a 54 mhz clock, the data is latched on the every rising edge. pixel input data 3ff 00 00 xy cb0 y0 y1 cr0 clkin figure 26c. input sequence in ps bit interleaved mode, eav/sav followed by cb0 data mpeg2 decoder p_vsync p_hsync p_blank clkin_a y[9:0] interlaced to progressive ycrcb 10 3 27mhz or 54mhz ycrcb ADV7314 figure 27. 1
rev. 0 ADV7314 e33e table i provides an overview of all possible input configurations. table i. input configurations input format total bits input video input pins subaddress register setting itu-r bt.656 01h 00h 48h 00h 01h 00h 48h 10h 16 y s9-s2 [msb = s9] 01h 00h crcb y9-y2 [msb = y9] 48h 08h 20 y s9-s0 [msb = s9] 01h 00h crcb y9-y0 [msb = y9] 48h 18h 8 ycrcb y9-y2 [msb = y9] 01h 80h 48h 00h 10 ycrcb y9-y0 [msb = y9] 01h 80h 48h 10h ps only 01h 10h 13h 40h 01h 10h 13h 44h 01h 70h 13h 40h 70h 10h 13h 44h 16 y y9-y2 [msb = y9] 01h 10h crcb c9-c2 [msb = c9] 13h 40h 20 y y9-y0 [msb = y9] 01h 10h crcb c9-c0 [msb = c9] 13h 44h 24 4:4:4 y y9-y2 [msb = y9] 01h 10h cb c9-c2 [msb = c9] 13h 00h cr s9-s2 [msb = s9] 30 4:4:4 y y9-y0 [msb = y9] 01h 10h cb c9-c0 [msb = c9] 13h 04h cr s9-s0 [msb = s9] hdtv only 16 4:2:2 y y9-y2 [msb = y9] 01h 20h crcb c9-y2 [msb = c9] 13h 40h 20 4:2:2 y y9-y0 [msb = y9] 01h 20h crcb c9-c0 [msb = c9] 13h 44h 24 4:4:4 y y9-y2 [msb = y9] 01h 20h cb c9-y2 [msb = c9] 13h 00h cr s9-s2 [msb = s9] 30 4:4:4 y y9-y0 [msb = y9] 01h 20h cb c9-c0 [msb = c9] 13h 04h cr s9-s0 [msb = s9] 24 4:4:4 g y9-y2 [msb = y9] 01h 10h or 20h bc 9-c2 [msb = c9] 13h 00h r s9-s2 [msb = s9] 15h 02h 30 4:4:4 g y9-y0 [msb = y9] 01h 10h or 20h bc 9-c0 [msb = c9] 13h 04h r s9-s0 [msb = s9] 15h 02h 8 4:2:2 ycrcb s9-s2 [msb = s9] 01h 40h 13h 40h 48h 00h 10 4:2:2 ycrcb s9-s0 [msb = s9] 01h 40h 13h 44h 48h 10h 8 4:2:2 ycrcb s9-s2 [msb = s9] 01h 30h or 50h or 60h 16 4:2:2 y y9-y2 [msb = y9] 13h 60h crcb c9-c2 [msb = c9] 48h 00h 10 4:2:2 ycrcb s9-s0 [msb = s9] 01h 30h or 50h or 60h 20 4:2:2 y y9-y0 [msb = y9] 13h 60h crcb c9-c0 [msb = c9] 48h 10h ycrcb s9-s2 [msb = s9] ycrcb s9-s0 [msb = s9] 8 [54 mhz clock] ycrcb y9-y2 [msb = y9] ycrcb y9-y0 [msb = y9] ycrcb y9-y2 [msb = y9] 4:2:2 4:2:2 ycrcb y9-y0 [msb = y9] hd rgb 8 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 10 [54 mhz clock] ycrcb y9-y2 [msb = y9] itu-r bt.656 and ps 10 4:2:2 ycrcb y9-y0 [msb = y9] itu-r bt.656 and ps itu-r bt.656 and ps or hdtv itu-r bt.656 and ps or hdtv 8 4:2:2 10 4:2:2 8 [27 mhz clock] 4:2:2 10 [27 mhz clock] 4:2:2
rev. 0 e34e ADV7314 output configuration these tables show which output signals are assigned to the dacs when the control bits are set accordingly. table ii. output configuration in sd only mode rgb/yuv output 02h, bit 5 sd dac output 1 42h, bit 2 sd dac output 2 42h, bit 1 dac a dac b dac c dac d dac e dac f 00 0 cvbs luma c hroma g b r 00 1g br cvbs luma chroma 01 0g luma c hroma cvbs b r 01 1 cvbs b r g luma chroma 10 0 cvbs luma c hroma y u v 10 1y uv cvbs luma chroma 11 0y luma c hroma cvbs u v 11 1 cvbs u v y luma chroma 0 1 table above with all luma/chroma instances swapped table as above luma/chroma swap 44h, bit 7 table iii. output configuration in hd/ps only mode hd input format hd rgb input 15h, bit 1 rgb/yprp b output 02h, bit 5 hd color swap 15h, bit 3 dac a dac b dac c dac d dac e dac f ycrcb 4:2:2 0 0 0 n/a n/a n/a g b r ycrcb 4:2:2 0 0 1 n/a n/a n/a g r b ycrcb 4:2:2 0 1 0 n/a n/a n/a y pb pr ycrcb 4:2:2 0 1 1 n/a n/a n/a y pr pb ycrcb 4:4:4 0 0 0 n/a n/a n/a g b r ycrcb 4:4:4 0 0 1 n/a n/a n/a g r b ycrcb 4:4:4 0 1 0 n/a n/a n/a y pb pr ycrcb 4:4:4 0 1 1 n/a n/a n/a y pr pb rgb 4:4:4 1 0 0 n/a n/a n/a g b r rgb 4:4:4 1 0 1 n/a n/a n/a g r b rgb 4:4:4 1 1 0 n/a n/a n/a g b r rgb 4:4:4 1 1 1 n/a n/a n/a g r b table iv. output configuration in simultaneous sd and hd/ps mode input formats rgb/yprp b output 02h, bit 5 hd color swap 15h, bit 3 dac a dac b dac c dac d dac e dac f itu-r bt.656 and hd ycrcb in 4:2:2 00 cvbs luma chroma g b r itu-r bt.656 and hd ycrcb in 4:2:2 01 cvbs luma chroma g r b itu-r bt.656 and hd ycrcb in 4:2:2 10 cvbs luma chroma y pb pr itu-r bt.656 and hd ycrcb in 4:2:2 11 cvbs luma chroma y pr pb
rev. 0 ADV7314 e35e timing modes hd async timing mode [subaddress 10h, bit 3,2] for any input data that do es not conform to the standards selectable in input mode, subaddress 01h, asynchronous tim- ing mode can be used to interface to the ADV7314. timing control signals for hsync v sync blank w pll s b av spte spte spte tr bt t t v clk active video programmable input timing analog output ab c 81 66 66 243 1920 horizontal sync e p_hsync p_vsync p_blank set address 10h, bit 6 to 1 d figure 28a. async timing mode?programming input control signals for smpte 295m compatibility active video 0 1 horizontal sync ab c d e clk p_hsync p_vsync p_blank set address 10h, bit 6 to 1 analog output figure 28b. async timing mode?programming input control signals for bilevel sync signal
rev. 0 e36e ADV7314 table v. async timing mode truth table reference in p_hsync p_vsync p_blank p_blank p p_blank a b p_blank h t r s b a h a t t h
rev. 0 ADV7314 e37e sd real-time control, subcarrier reset, and timing reset [subaddress 44h, bit 2,1] together with the rtc_scr_tr pin and sd mode register 3, the ADV7314 can be used in timing r eset mode, subcarrier phase r eset mode, or rtc mode. timing reset mode a timing reset is achieved in a low-to-high transition on the rtc_scr_tr pin (pin 31). in this state, the horizontal and vertical counters will remain reset. on releasing this pin (set to low), the internal counters will commence counting again, the field count will start on field 1, and the subcarrier phase will be reset. the minimum time the pin has to be held high is one clock cycle; otherwise this reset signal might not be recognized. this timing reset applies to the sd timing counters only. subcarrier phase reset a low-to-high transition on the rtc_scr_tr pin (pin 31) will reset the subcarrier phase to zero on the field following the subcarrier phase reset when the sd rtc/tr/scr control bits at address 44h are set to 01. this reset signal will have to be held high for a minimum of one clock cycle. since the field counter is not reset, it is recommended that the reset signal should be applied in field 7 [pal] or field 3 [ntsc]. the reset of the phase will then occur on the next field, i.e., field 1, being lined up correctly with the internal counters. the field count register at address 7bh can be used to identify the number of the active field. rtc mode in rtc mode, the ADV7314 can be used to lock to an external video source. the real-time control mode allows the ADV7314 to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device that outputs a digital datastream in the rtc format (such as an adv7183a video decoder, see figure 31), the part will auto- matically change to the compensated subcarrier frequency on a line by line basis. this digital datastream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when using this mode. display no timing reset applied timing reset applied start of field 4 or 8 f sc phase = field 4 or 8 f sc phase = field 1 timing reset pulse 307 310 307 1 2 3 4 5 6 7 21 313 320 display start of field 1 figure 29. timing reset timing diagram no f sc reset applied f sc phase = field 4 or 8 307 310 313 320 display start of field 4 or 8 f sc reset applied f sc reset pulse f sc phase = field 1 307 310 313 320 display start of field 4 or 8 figure 30. subcarrier reset timing diagram
rev. 0 e38e ADV7314 reset sequence a reset is activated with a high-to-low transition on the reset p t av reset s vcr rw s s b v vcr rw s c w vcr rw s b vsync vsync t s lcc1 gll p19?p10 adv7183a video decoder composite video e.g., vcr or cable clkin_a rtc_scr_tr dac a dac b dac c dac d dac e dac f y9-y0/s9?s0 * rtc low h/l transition count start 128 time slot 01 13 0 14 bits subcarrier phase 14 21 19 f sc pll increment 1 valid sample invalid sample 8/line locked clock 6768 4 bits reserved 0 sequence bit 2 reset bit 3 reserved 5 bits reserved ADV7314 notes 1 f sc pll increment is 22 bits long. value loaded into ADV7314 f sc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7314. 2 sequence bit pal: 0 = line normal, 1 = line inverted; ntsc: 0 = no change 3 sequence bit reset ADV7314 dds * selected by register address 01h bit 7 figure 31. rtc timing and connections xxxxxx xxxxxx off digital timing signals suppressed valid video timing active reset digital timing dacs a, b, c pixel data valid figure 32. reset ts
rev. 0 ADV7314 e39e vertical blanking interval the ADV7314 accepts input data that contains vbi data [e.g., cgms, wss, vits] in sd and hd modes. for smpte 293m [525p] standards, vbi data can be inserted on lines 13 to 42 of each frame, or lines 6 to 43 for itu-r bt.1358 [625p] standard. for sd ntsc, this data can be present on lines 10 to 20, and in pal on lines 7 to 22. if vbi is disabled [address 11h, bit 4 for hd; address 43h, bit 4 for sd], vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave modes. in slave mode 0, if vbi is enabled, the blanking bit in the eav/ sav code is overwritten; it is possible to use vbi in this timing mode as well. in slave mode 1 or 2, the blank a a b vb av av vb cs vb cs s s r s c t subcarrier frequency gister subcarrier frequency value mhz clk cycles in one video line re = # #27 2 23 for example, in ntsc mode, subcarrier frequencyvalue = ? ? ? = 227 5 1716 2 569408542 23 . sd f sc register 0: 1eh sd f sc register 1: 7ch sd f sc register 2: f0h sd f sc register 3: 21h refer to the mpu port description section for more details on how to access the subcarrier frequency registers. square pixel timing [register 42h, bit 4] in square pixel mode, the following timing diagrams apply. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data ( hanc) 4 clock 4 clock 272 clock 1280 clock 4 clock 4 clock 344 clock 1536 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y figure 33. eav/sav embedded timing field pixel data pal = 44 clock cycles ntsc = 44 clock cycles pal = 136 clock cycles ntsc = 208 clock cycles cb y cr y h sync b lank apt
rev. 0 e40e ADV7314 filter section table vi shows an overview of the programmable filters avail- able on the ADV7314. table vi. selectable filters of the ADV7314 filter subaddress sd luma lpf ntsc 40h sd luma lpf pal 40h sd luma notch ntsc 40h sd luma notch pal 40h sd luma ssaf 40h sd luma cif 40h sd luma qcif 40h sd chroma 0.65 mhz 40h sd chroma 1.0 mhz 40h sd chroma 1.3 mhz 40h sd chroma 2.0 mhz 40h sd chroma 3.0 mhz 40h sd chroma cif 40h sd chroma qcif 40h sd uv ssaf 42h hd chroma input 13h hd sinc filter 13h hd chroma ssaf 13h hd sinc filter frequency ( mhz ) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 figure 35. hd sinc filter enabled frequency ( mhz ) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 figure 36. hd sinc filter disabled
rev. 0 ADV7314 e41e sd internal filter response [subaddress 40h; subaddress 42, bit 0] the y filter supports several different frequency responses includ- ing two low-pass responses, two notch responses, an extended (ssaf) response, with or without gain boost/attenuation, a cif response and a qcif response. the uv filter supports several different frequency responses, including six low -pass responses, a cif response and a qcif res ponse, as can be seen in the typical performance characteristics graphs. if sd ssaf gain is enabled, there are 12 possible responses in the range from e4 db to +4 db [subaddress 47h, bit 4]. the desired response can be chosen by the user by programming the correct value via the i 2 c [subaddress 62h]. the variation of frequency responses can be seen in the typical performance characteristics graphs. table vii. internal filter specifications pass-band ripple 3 db bandwidth filter (db) (mhz) luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif monotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 1 pass-band ripple refers to the maximum fluctuations from the 0 db response in the pass band, measured in db. the pass band is defined to have 0 hz to fc (hz) frequency limits for a low-pass filter, 0 hz to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, f2 are the e3 db points. 2 3 db bandwidth refers to the e3 db cutoff frequency. in addition to the chroma filters listed in table vii, the ADV7314 contains an ssaf filter specifically designed for and applicable to the color difference component outputs, u and v. this filter has a cutoff frequency of about 2.7 mhz and e40 db at 3.8 mhz, as can be seen in figure 37. this filter can be controlled with address 42h, bit 0. if this filter is disabled, the selectable chroma filters shown in table vii can be used for the cvbs or luma/chroma signal. frequency (mhz) 0 gain (db) ?10 ?30 ?50 ?60 ?20 ?40 6 5 4 3 2 1 0 extended uv filter mode figure 37. uv ssaf filter
rev. 0 e42e ADV7314etypical performance characteristics frequency (mhz) prog scan pr/pb response. linear interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 1. ps e uv 8 frequency (mhz) y response in ps oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 2. ps ey 8 frequency (mhz) pr/pb response in hdtv oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 tpc 3. hdtv e uv 2 frequency (mhz) prog scan pr/pb response. ssaf interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 tpc 4. ps e uv 8 frequency (mhz) y passband in ps oversampling mode gain (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?3.0 12 246810 0 tpc 5. ps e y 8 frequency (mhz) y response in hdtv oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 tpc 6. hdtv e y 2
rev. 0 ADV7314 e43e frequency ( mhz ) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 7. luma ntsc low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 8. luma ntsc notch filter frequency (mhz) y response in sd oversampling mode gain (db) 0 ?50 ?80 0204 06080 100 120 140 160 180 200 ?10 ?40 ?60 ?70 ?20 ?30 tpc 9. y?16 frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 10. luma pal low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 11. luma pal notch filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 tpc 12. luma ssaf filter up to 12 mhz
rev. 0 e44e ADV7314 frequency (mhz) 4 01234 7 magnitude (db) 2 ?2 ?6 ?8 ?12 0 ?4 5 ?10 6 tpc 13. luma ssaf filter?programmable responses frequency ( mhz ) 01234 7 magnitude (db) 1 0 ?2 ?3 ?5 ?1 5 ?4 6 tpc 14. luma ssaf filter?programmable attenuation frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 15. luma qcif lp filter frequency ( mhz ) 01234 7 magnitude (db) 5 4 2 1 ?1 3 5 0 6 tpc 16. luma ssaf filter?programmable gain frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 17. luma cif lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 18. chroma 3.0 mhz lp filter
rev. 0 ADV7314 e45e frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 19. chroma 2.0 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 20. chroma 1.0 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 21. chroma cif lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 22. chroma 1.3 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 23. chroma 0.65 mhz lp filter frequency (mhz) 0 02468 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 tpc 24. chroma qcif lp filter
rev. 0 e46e ADV7314 color controls and rgb matrix hd/ps y level, cr level, cb level [subaddress 16he18h] three 8-bit registers at address 16h, 17h, 18h are used to program the output color of the internal hd test pattern generator, whether it is the lines of the cross hatch pattern or the uniform field test pattern. they are not functional as color controls on external pixel data input. for this purpose, the rgb matrix is used. the standard used for the values for y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the itu-r bt.601e4 standard. table viii shows sample color values to be programmed into the color registers when output standard selection is set to eia 770.2. table viii. sample color values for eia770.2 output standard selection sample color y color cr color cb color value value value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128(80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) hd rgb matrix [subaddress 03he09h] when the programmable rgb matrix is disabled [address 02h, bit 3], the internal rgb matrix takes care of all ycrcb to yuv or rgb scaling according to the input standard programmed into the device. when the programmable rgb matrix is enabled, the color components are converted according to the 1080i standard [smpte 274m]: y' = 0.2126 r' + 0.7152 g' + 0.0722 b' cr' = [0.5/(1 ?0.0722)] ( b'?') cr' = [0.5/(1 ?0.2126)] ( r'?') this is reflected in the preprogrammed values for gy = 138bh, gu = 93h, gv = 3b, bu = 248h, rv = 1f0. if another input standard is used, the scale values for gy, gu, gv, bu, and rv have to be adjusted according to this input standard. the user must consider that the color component conversion might use different scale values. for example, smpte 293m uses the following conversion: y' = 0.299 r' + 0.587 g' + 0.114 b' cb' = [0.5 / (1 ?0.114)] ( b'?') cr' = [0.5 / (1 ?0.299)] ( r'?') the programmable rgb matrix can be used to control the hd output levels in cases where the video output does not conform to standard due to altering the dac output stages such as ter- mination resistors. the programmable rgb matrix is used for external hd data and is not functional when the hd test pattern is enabled. programming the rgb matrix the rgb matrix should be enabled [address 02h, bit 3], the output should be set to rgb [address 02h, bit 5], sync on prpb should be disabled [address 15h, bit 2], sync on rgb is optional [address 02h, bit 4]. gy at addresses 03h and 05h control the output levels on the green signal, bu at 04h and 08h control the blue signal output levels, and rv at 04h and 09h control the red output levels. to control yprpb output levels, yuv output should be enabled [address 02h, bit 5]. in this case gy [address 05h; address 03, bit 0?] is used for the y output, rv [address 09; address 04, bit 0?] is used for the pr output and bu [address 08h; address 04h, bit 23] is used for the pb output. if rgb output is selected the rgb matrix scaler uses the fol- lowing equations: g = gy y + gu pb + gv pr b = gy y + bu pb r = gy y + rv pr if yuv output is selected the following equations are used: y = gy y u = bu pb v = rv pr on power-up, the rgb matrix is programmed with default values: table ix. rgb matrix default values address default 03h 03h 04h f0h 05h 4eh 06h 0eh 07h 24h 08h 92h 09h 7ch when the programmable rgb matrix is not enabled, the ADV7314 automatically scales ycrcb inputs to all standards supported by this part. sd luma and color control [subaddresses 5ch, 5dh, 5eh, 5fh] sd y scale, sd cr scale, and sd cb scale are 10-bit control registers to scale the y, u, and v output levels. each of these registers represents the value required to scale the u or v level from 0.0 to 2.0 and y level from 0.0 to 1.5 of its initial level. the value of these 10 bits is calculated using the following equation: y, u, or v scalar value = scale factor 512 for example: scale factor = 1.18 y, u, or v scale value = 1.18 512 = 665.6 y, u, or v scale value = 665 (rounded to the nearest integer) y, u, or v scale value = 1010 0110 01b address 5ch, sd lsb register = 15h address 5dh, sd y scale register = a6h address 5eh, sd v scale register = a6h address 5fh, sd u scale register = a6h
rev. 0 ADV7314 e47e sd hue adjust value [subaddress 60h] the hue adjust value is used to adjust the hue on the composite and chroma outputs. these eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. the ADV7314 provides a range of 22.5 4 0 17578125 128 151 97 . ? ? ? += = dh * * rounded to the nearest integer. to adjust the hue by ? - ? ? ? += = 4 0 17578125 128 105 69 . dh * * rounded to the nearest integer. sd brightness control [subaddress 61h] the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the scaled y data. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and pal, the setup can vary from ?.5 ire to +15 ire. the brightness control register is an 8-bit register. seven bits of this 8-bit register are used to control the brightness level. this brightness level can be a positive or negative value. for example: standard: ntsc with pedestal. to add +20 ire brightness level, write 28h to address 61h, sd brightness. [] [.] [. ][.] sd brightnessvalue h irevalue h hhh = = = = 2 015631 20 2 015631 40 31262 28 standard: pal. to add e7 ire brightness level, write 72h to address 61h, sd brightness. ire value b o twos complement b h [] = [] = [] = [] = [] = 2 015631 72 015631 14 109417 0001110 0001110 1110010 72 . .. int table x. brightness control values * setup setup level in level in setup ntsc with ntsc no level in sd pedestal pedestal pal brightness 22.5 ire 15 ire 15 ire 1eh 15 ire 7.5 ire 7.5 ire 0fh 7.5 ire 0 ire 0 ire 00h 0 ire ?.5 ire ?.5 ire 71h * values in the range from 3fh to 44h might result in an invalid output signal. sd brightness detect [subaddress 7ah] the ADV7314 allows monitoring of the brightness level of the incoming video data. brightness detect is a read-only register. double buffering [subaddress 13h, bit 7; subaddress 48h, bit 2] double buffered registers are updated once per field on the falling edge of the vsync h h a b h cs s s a b s y s s v s s s b ntsc without pedestal no setup value added positive setup value added 100 ire 0 ire negative setup value added ?7.5 ire +7.5 ire figure 38. examples for brightness control values
rev. 0 e48e ADV7314 programmable dac gain control dacs a, b, and c are controlled by register 0a. dacs d, e, and f are controlled by register 0b. the i 2 c control registers will adjust the output signal gain up or down from its absolute level. case b 700mv 300mv negative gain programmed in dac output level registers, subaddress 0ah, 0bh case a gain programmed in dac o/p level registers, subaddress 0ah, 0bh 700mv 300mv figure 39. programmable dac gain?positive and negative gain in case a, the video output signal is gained. the absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. the overall gain of the signal is increased from the reference signal. in case b, the vi deo output signal is reduced. the absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. the overall gain of the signal is reduced from the reference signal. the range of this feature is specified for 7.5% of the nominal output from the dacs. for example, if the output current of the dac is 4.33 ma, the dac tune feature can change this output current from 4.008 ma (e7.5%) to 4.658 ma (+7.5%). the reset value of the vid_out_ctrl registers is 00h e> nominal dac output current. table xi is an example of how the output current of the dacs varies for a nominal 4.33 ma output current. table xi. dac register current 0ah or 0bh (ma) % gain 0100 0000 (40h) 4.658 7.5000 0011 1111 (3fh) 4.653 7.3820 0011 1110 (3eh) 4.648 7.3640 ... ... ... ... ... ... 0000 0010 (02h) 4.43 0.0360 0000 0001 (01h) 4.38 0.0180 0000 0000 (00h) 4.33 0.0000 (i 2 c reset value, nominal) 1111 1111 (ffh) 4.25 e0.0180 1111 1110 (feh) 4.23 e0.0360 ... ... ... ... ... ... 1100 0010 (c2h) 4.018 e7.3640 1100 0001 (c1h) 4.013 e7.3820 1100 0000 (c0h) 4.008 e7.5000
rev. 0 ADV7314 e49e gamma correction [subaddress 24he37h for hd, subaddress 66he79h for sd] gamma correction is available for sd and hd video. for each standard there are 20 8-bit registers. they are used to program the gamma correction curves a and b. hd gamma curve a is programmed at addresses 24he2dh, hd gamma curve b at 2ehe37h. sd gamma curve a is programmed at addresses 66he6fh, and sd gamma curve b at addresses 70he79h. generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wher- ever nonlinear processing is used. gamma correction uses the function signal signal out in = () g where location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input gamma corrected amplitude signal output gamma correction block output to a ramp input figure 40. signal input (ramp) and signal output for gamma 0.5 for the length of 16 to 240, the gamma correction curve has to be calculated as follows: y = x y = gamma corrected output. x = linear input signal. y have to be calculated using the following formula: y x n n = - () ? ? ? ? ? - () + () e16 240 16 240 16 16 g where: x ( n ?6) = value for x along x-axis at points. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. y n = value for y along the y-axis, which has to be written into the gamma correction register. for example: y 24 = [(8 / 224) 0.5 224] + 16 = 58 * y 32 = [(16 / 224) 0.5 224] + 16 = 76 * y 48 = [(32 / 224) 0.5 224] + 16 = 101 * y 64 = [(48 / 224) 0.5 224] + 16 =120 * y 80 = [(64 / 224) 0.5 224] + 16 =136 * y 96 = [(80 / 224) 0.5 224] + 16 = 150 * y 128 = [(112 / 224) 0.5 224] + 16 = 174 * y 160 = [(144 / 224) 0.5 224] + 16 = 195 * y 192 = [(176 / 224) 0.5 224] + 16 = 214 * y 224 = [(208 / 224) 0.5 224] + 16 = 232 * * rounded to the nearest integer the gamma curves in figure 41 are examples only; any user defined curve is acceptable in the range of 16 to 240. location 0 0 50 100 150 200 250 300 50 100 150 200 250 gamma corrected amplitude gamma correction block to a ramp input for various gamma values 0.3 0.5 1.5 1.8 signal input figure 41. signal input (ramp) and selectable gamma output curves
rev. 0 e50e ADV7314 hd sharpness filter control and adaptive filter control [subaddress 20h, 38he3dh] there are three filter modes available on the ADV7314: sharpness filter mode and two adaptive filter modes. hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 42, the following register settings must be used: hd sharpness filter must be enabled and hd adaptive filter enable must be disabled. to select one of the 256 individual responses, the according gain values for each filter, which range from e8 to +7, must be pro- grammed into the hd sharpness filter gain register at address 20h. hd adaptive filter mode the hd adaptive filter threshold a, b, c registers, the hd adaptive filter gain 1, 2, 3 registers, and the hd sharpness filter gain register are used in adaptive filter mode. to activate the adaptive filter control, hd sharpness filter must be enabled and hd adaptive filter gain must be enabled. frequency (mhz) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter a response (gain ka) frequency (mhz) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 filter b response (gain kb) frequency (mhz) magnitude response (linear scale) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 024681012 input signal: step frequency response in sharpness filter mode with ka = 3 and kb = 7 sharpness and adaptive filter control block figure 42. sharpness and adaptive filter control block frequency response in sharpness filter mode with ka = +3 and kb = +7 the derivative of the incoming signal is compared to the three programmable threshold values: hd adaptive filter threshold a, b, c. the recommended threshold range is from 16 to 235 although any value in the range of 0 to 255 can be used. the edges can then be attenuated with the settings in hd adaptive filter gain 1, 2, 3 registers and hd sharpness filter gain register. according to the settings of the hd adaptive filter mode con- trol, there are two adaptive filter modes available: 1. mode a is used when adaptive filter mode is set to 0. in this case, filter b (lpf) will be used in the adaptive filter block. also, only the programmed values for gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, 3 are applied when needed. the gain a values are fixed and cannot be changed. 2. mode b is used when adaptive filter gain is set to 1. in this mode, a cascade of filter a and filter b is used. both set- tings for gain a and gain b in the hd sharpness filter gain, hd adaptive filter gain 1, 2, 3 become active when needed.
rev. 0 ADV7314 e51e f e d a b c 1 r4 r2 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 9.99978ms r2 r1 1 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 9.99978ms figure 43. hd sharpness filter control with different gain settings for hs sharpness filter gain value hd sharpness filter and adaptive filter application examples hd sharpness filter application the hd sharpness filter can be used to enhance or attenuate the y video output signal. the following register settings were used to achieve the results shown in the figures below. input data was generated by an external signal source. table xii. register reference in address setting figure 43 00h fch 01h 10h 02h 20h 10h 00h 11h 81h 20h 00h a 20h 08h b 20h 04h c 20h 40h d 20h 80h e 20h 22h f the effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern. table xiii. address register setting 00h fch 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h in toggling the sharpness filter enable bit [address 11h, bit 7], it can be seen that the line contours of the cross hatch pattern change their sharpness.
rev. 0 e52e ADV7314 adaptive filter control application figures 44 and 45 show a typical signal to be processed by the adaptive filter control block. : 692mv @: 446mv : 332ns @: 12.8ms figure 44. input signal to adaptive filter control : 692mv @: 446mv : 332ns @: 12.8ms figure 45. output signal after adaptive filter control the following register settings were used to obtain the results shown in figure 45, i.e., to remove the ringing on the y signal. input data was generated by an external signal source. table xiv. address register setting 00h fch 01h 38h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h * all other registers at normal settings. when changing the adaptive filter mode to mode b, [address 15h, bit 6], the following output can be obtained: : 674mv @: 446mv : 332ns @: 12.8ms figure 46. output signal from adaptive filter control the adaptive filter control can also be demonstrated using the internally generated cross hatch test pattern and toggling the adaptive filter control bit [address 15h, bit 7]. table xv. address register setting 00h fch 01h 38h 02h 20h 10h 00h 11h 85h 15h 80h 20h 00h 38h ach 39h 9ah 3ah 88h 3bh 28h 3ch 3fh 3dh 64h
rev. 0 ADV7314 e53e sd digital noise reduction [subaddress 63h, 64h, 65h] dnr is applied to the y data only. a filter block selects the high frequency, low amplitude components of the incoming signal [dnr input select]. the absolute value of the filter output is compared to a programmable threshold value [dnr threshold control]. there are two dnr modes available: dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. a programmable amount [coring gain border, coring gain data] of this noise signal will be subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter out- put is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal [coring gain border, coring gain data] will be added to the origi- nal signal in order to boost high frequency components and to sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 pixels block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold ? input filter block filter output < threshold dnr out + + main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y data input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold ? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y data input ? + figure 47. dnr block diagram the digital noise reduction registers are three 8-bit registers. they are used to control the dnr processing. coring gain border [address 63h, bits 3e0] these four bits are assigned to the gain factor applied to border areas. in dnr mode, the range of gain values is 0e1, in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode the range of gain values is 0e0.5, in increments of 1/16. this factor is applied to the dnr filter output which lies above the threshold range. the result is added to the original signal. coring gain data [address 63h, bits 7-4] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode the range of gain values is 0e1, in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0e0.5, in increments of 1/16. this factor is applied to the dnr filter output, which lies above the threshold range. the result is added to the original signal. oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo dnr27 ? dnr24 = 01h offset caused by variations in input timing apply border coring gain apply data coring gain figure 48. dnr block offset control dnr threshold [address 64h, bits 5e0] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border area [address 64h, bit 6] in setting this bit to a logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to a logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (n tsc) 8 8 pixel block 8 8 pixel block 2 pixel border data figure 49. dnr border area
rev. 0 e54e ADV7314 block size control [address 64h, bit 7] this bit is used to select the size of the data blocks to be processed. setting the block size control function to a logic 1 defines a 16 pixel 16 pixel data block; a logic 0 defines an 8 pixel 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. dnr input select control [address 65h, bit 2e0] three bits are assigned to select the filter that is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that will be dnr processed. f igure 50 shows the filter responses selectable with this control. filter c filter b filter a filter d frequency (hz) 0 012 3 456 0.2 0.4 0.6 magnitude 0.8 1.0 figure 50. dnr input select dnr mode control [address 65h, bit 4] this bit controls the dnr mode selected. a logic 0 selects dnr mode; a logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. the overall effect is that the signal will be boosted (similar to using extended ssaf filter). block offset control [address 65h, bits 7e4] four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
rev. 0 ADV7314 e55e sd active video edge [subaddress 42h, bit 7] when the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum transitions on these pixels are not possible. the scaling factors are 1/8, 1/2, 7/8. all other active video passes through unprocessed. 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire luma channel with ac tive video edge disabled luma channel with a ctive video edge enabled figure 51. example for active video edge functionality volts 024 f2 l135 6810 12 ire:flt ?50 0 0 50 100 0.5 figure 52. address 42h, bit 7 = 0 volts 02 ?2 4 6 8 10 12 f2 l135 ire:flt ?50 0 50 100 0 0.5 figure 53. address 42h, bit 7 = 1 sav/eav step edge control the ADV7314 can control fast rising and falling signals at the start and end of active video to minimize ringing. an algorithm monitors sav and eav and governs when the edges are too fast. the result will be reduced ringing at the start and end of active video for fast transitions. subaddress 42h, bit 7 = 1 enables this feature.
rev. 0 e56e ADV7314 board design and layout considerations dac termination and layout considerations the ADV7314 contains an on-board voltage reference. the ADV7314 can be used with an external v ref (ad1580). the r set resistors are connected between the r set pins and agnd and are used to control the full-scale output current and therefore the dac voltage output levels. for full-scale output, r set must have a value of 3040 w . the r set values should not be changed. r load has a value of 150 w with a 4 >6.5 20.5 sd 16 >6.5 209.5 ps 1 >12.5 14.5 ps 8 >12.5 203.5 hdtv 1 >30 44.25 hdtv 2 >30 118.5 600 300 3 4 1 22pf 300 dac output 75 bnc output 2.2 h 1.8k figure 54. example for output filter for sd, 16 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 ?240 16n 14n 12n 10n 8n 6n 4n 2n 0 1m 10m 100m frequency (hz) circuit frequency response group delay (sec) phase (deg) magnitude (db) gain (db) figure 55. filter plot for output filter for sd, 16
rev. 0 ADV7314 e57e 600 3 4 1 22pf 300 22pf 300 dac output 75 bnc output 3.3 h 1.8k figure 56. example for output filter for ps, 8 oversampling 82pf 33pf 75 dac output 220nh 470nh 500 3 4 1 bnc output 500 300 3 4 1 75 figure 57. example for output filter for hdtv, 2 oversampling table xvii shows possible output rates from the ADV7314. table xvii. input mode pll output address 01h, bit 6e4 address 00h, bit 1 rate sd only off 27 mhz (2 ) on 216 mhz (16 ) ps only off 27 mhz (1 ) on 216 mhz (8 ) hdtv only off 74.25 mhz (1 ) on 148.5 mhz (2 ) 0 ?12 ?6 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 198 118 158 77.6 37.6 0 ?42.4 ?82.4 ?122 ?162 ?202 20n 16n 18n 14n 12n 10n 8n 6n 4n 2n 0 1m 10m 100m 1g frequency (hz) circuit frequency response magnitude (db) phase (deg) gain (db) group delay (sec) group delay (sec) figure 58. filter plot for output filter for ps, 8 oversampling 0 ?10 ?20 ?30 ?40 ?50 ?60 480 360 240 120 0 ?120 ?240 18n 15n 12n 9n 6n 3n 0 1m 10m 100m 1g frequency (hz) circuit frequency response group delay (sec) phase (deg) magnitude (db) gain (db) figure 59. example for output filter hdtv, 2 oversampling
rev. 0 e58e ADV7314 pc board layout considerations the ADV7314 is optimally designed for lowest noise perfor- mance, for both radiated and conducted noise. to complement the excellent noise performance of the ADV7314, it is impera- tive that great care be given to the pc board layout. the layout should be optimized for lowest noise on the ADV7314 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd, v dd and dgnd, and v dd_io and gnd_io pins should be kept as short as possible to minimized inductive ringing. it is recommended that a 4-layer printed circuit board is used with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. com- ponent placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. there should be a separate analog ground plane and a separate digital ground plane. power planes should encompass a digital power plane and an analog power plane. the analog power plane should contain the dacs and all associated circuitry, v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually con- nected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). the dac termi- nation resistors should be placed as close as possible to the dac outputs and should overlay the pcb?s ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. to avoid crosstalk between the dac outputs, it is recommended to leave as much space as possible between the tracks of the individual dac output pins. the addition of ground tracks between outputs is also recommended. supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 10 nf and 0.1 m f ceramic capacitors. each of group of v aa , v dd , or v dd_io pins should be individually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus mini- mizing lead inductance. a 1 m f tantalum capacitor is recommended across the v aa supply in addition to a 10 nf ceramic capacitor. see figure 60. digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the ADV7314 should be avoided to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not to the analog power plane. analog signal interconnect the ADV7314 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. for optimum performance, the analog outputs should each be source and load terminated, as shown in figure 60. the termi- nation resistors should be as close as possible to the ADV7314 to minimize reflections. for optimum performance, it is recommended that all decoupling and external components relating to the ADV7314 be located on the same side of the pcb and as close as possible to the ADV7314. any unused inputs should be tied to ground.
rev. 0 ADV7314 e59e s_hsync s0?s9 s_vsync s blank c0?c9 y0?y9 p_hsync p_vsync p_blank reset clkin_b clkin_a ext_lf gnd_io agnd dgnd r set1 r set2 alsb sclk dac f dac e dac d dac c dac b dac a v ref v dd _ io v dd v aa comp2 comp1 150 150 150 150 150 5k sda 11, 57 3040 3040 5k v dd _ io 5k v dd _ io 5k v dd _ io 3.9nf 680 820pf v aa 4.7 f 150 v aa unused inputs should be grounded. 4.7k v aa v aa 0.1 f 0.1 f 0.1 f v aa 1 f 10nf 0.1 f 10nf 10nf 10, 56 v dd _ io v dd mpu bus ADV7314 power supply decoupling for each power supply group 100nf 1.1k v aa recommended external ad1580 for optimum performance v dd_io i 2 c selection here determines device address 100 100 figure 60. ADV7314 circuit layout
rev. 0 e60e ADV7314 appendix 1?copy generation management system ps cgms data registers 2e0 [subaddress 21h, 22h, 23h] ps cgms is available in 525p mode conforming to cgms-a eia-j cpr1204-1, transfer method of video id information using vertical blanking interval (525p system), march 1998, and iec61880, 1998, video systems (525/60)?vide o and accom- panied data using the vertical blanking interval?analog interface. when ps cgms is enabled [subaddress 12h, bit 6 = 1], cgms data is inserted on line 41. the ps cgms data registers are at addresses 21h, 22h, and 23h. sd cgms data registers 2e0 [subaddress 59h, 5ah, 5bh] the ADV7314 supports copy generation management system (cgms), conforming to the standard. cgms data is transmit- ted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can be transmitted only when the ADV7314 is configured in ntsc mode. the cgms data is 20 bits long, and the function of each of these bits is as shown in t able xviii. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit; see figure 62. hd/ps cgms [address 12h, bit 6] the ADV7314 supports copy generation management s ystem (cgms) in hdtv mode ( 720p and 1080i) in accor dance with eiaj cpr-1204-2. the hd cgms data registers can be found at address 021h, 22h, 23h. function of cgms bits word 0e6 bits; word 1e4 bits; word 2e6 bits; crc 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) 720p system cgms data is applied to line 24 of the luminance vertical blanking interval. 1080i system cgms data is applied to line 19 and on line 582 of the lumi- nance vertical blanking interval. cgms functionality if sd cgms crc [address 59h, bit 4] or ps/hd cgms crc [subaddress 12h, bit 7] is set to a logic 1, the last six bits, c19ec14, which comprise the 6-bit crc check sequence, are calculated automatically on the ADV7314 based on the lower 14 bits (c0ec13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if sd cgms crc [address 59h, bit 4] or ps/hd cgms crc [ad- dress 12h, bit 7] is set to a logic 0, all 20 bits (c0ec19) are output directly from the cgms registers (no crc calculated, must be calculated by the user). table xviii. bit function word0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 undefined word0 b4, b5, b6 identification information about video and other signals (e.g., audio) word1 b7, b8, b9, b10 identification signal incidental to word 0 word2 b11, b12, b13, b14 identification signal and information incidental to word 0
rev. 0 ADV7314 e61e c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence 21.2 s 0.22 s 22t ref 5.8 s 0.15 s 6t 0mv ?300mv 70% 10% t = 1/(f h 33) = 963ns f h = horizontal scan frequency t 30ns + 700mv bit 1 bit 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit 20 figure 61. progressive scan cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence 49.1 s 0.5 s ref 11.2 s 0 ire ?40 ire +70 ire +100 ire 2.235 s 20ns figure 62. standard definition cgms waveform crc sequence c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 ref 4t 3.128 s 90ns 17.2 s 160ns 22t t = 1/(f h 1650/58) = 781.93ns f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% + 700mv bit 1 bit 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit 20 figure 63. hdtv 720p cgms waveform c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 crc sequence ref 4t 4.15 s 60ns 22.84 s 210ns 22t t = 1/(f h 2200/77) = 1.038 s f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% + 700mv bit 1 bit 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit 20 figure 64. hdtv 1080i cgms waveform
rev. 0 e62e ADV7314 bit description bit 0ebit 2 aspect ratio/format/position bits bit 3 is odd parity check of bit 0ebit 2 b0, b1, b2, b3 aspect ratio format position 0 0 0 1 4:3 full format not applicable 1 0 0 0 14:9 letterbox center 0 1 0 0 14:9 letterbox top 1 1 0 1 16:9 letterbox center 0 0 1 0 16:9 letterbox top 1 0 1 1 >16:9 letterbox center 0 1 1 1 14:9 full format center 1 1 1 0 16:9 n/a n/a b4 0c amera mode 1f ilm mode b5 0 standard coding 1m otion adaptive color plus table xix. function of wss bits bit description b6 0n o helper 1m odulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0n o surround sound information 1 surround sound mode b12 reserved b13 reserved appendix 2?sd wide screen signaling [subaddress 59h, 5ah, 5bh] the ADV7314 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can be transmitted only when the ADV7314 is configured in pal mode. the wss data is 14 bits long, and the function of each of these bits is as shown in table xix. the wss data is preceded w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 active video r un-in se quence st art c ode 500mv 11.0 s 38.4 s 42.5 s figure 65. wss waveform diagram by a run-in sequence and a start code (see figure 65). if sd wss [address 59h, bit 7] is set to a logic 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 m s from the falling edge of hsync wss l s b
rev. 0 ADV7314 e63e appendix 3?sd closed captioning [subaddress 51he54h] the ADV7314 supports closed captioning conforming to the standard television synchronizing waveform for color transmis- sion. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. 16 bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in the sd closed captioning registers [address 53he54h]. the ADV7314 also supports the extended closed captioning operation, which is active during even fields and is encoded on scan line 284. the data for this operation is stored in the sd closed captioning registers [address 51he52h]. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the ADV7314. all pixels inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the ADV7314 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other two byte deep buffering systems. the data must be loaded one line before (line 20 or line 283) it is out- put on line 21 and line 284. a typical implementation of this method is to use vsync l h w s t a r t p a r i t y p a r i t y d0?d6 d0?d6 10.5 0.25 s 12.91 s 7 cycles of 0.5035mhz clock run-in reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 50 ire 40 ire 10.003 s 27.382 s 33.764 s byte 1 byte 0 two 7-bit + parity ascii characters (data) figure 66. closed captioning waveform, ntsc
rev. 0 e64e ADV7314 appendix 4?test patterns the ADV7314 can generate sd and hd test patterns. ch2 200mv m 10.0 sa ch2 1.20v t 30.6000 s 2 t figure 67. ntsc color bars ch2 200mv m 10.0 sa ch2 1.21v t 30.6000 s 2 t figure 68. pal color bars ch2 100mv m 10.0 s ch2 even t 1.82600ms 2 t figure 69. ntsc black bar (e21 mv, 0 mv, 3.5 mv, 7 mv, 10.5 mv, 14 mv, 18 mv, 23 mv) ch2 100mv m 10.0 s ch2 even t 1.82600ms 2 t figure 70. pal black bar (e21 mv, 0 mv, 3.5 mv, 7 mv, 10.5 mv, 14 mv, 18 mv, 23 mv) ch2 200mv m 4.0 s ch2 even t 1.82944ms 2 t figure 71. 525p hatch pattern ch2 200mv m 4.0 s ch2 even t 1.84208ms 2 t figure 72. 625p hatch pattern
rev. 0 ADV7314 e65e ch2 200mv m 4.0 s ch2 even t 1.82872ms 2 t figure 73. 525p field pattern ch2 200mv m 4.0 s ch2 even t 1.84176ms 2 t figure 74. 525p black bar (e35 mv, 0 mv, 7 mv, 14 mv, 21 mv, 28 mv, 35 mv) ch2 100mv m 4.0 s ch2 even t 1.82936ms 2 t figure 75. 625p field pattern ch2 100mv m 4.0 s ch2 even t 1.84176ms 2 t figure 76. 625p black bar (e35 mv, 0 mv, 7 mv, 14 mv, 21 mv, 28 mv, 35 mv) the following register settings are used to generate an sd ntsc cvbs output on dac a. register subaddress setting 00h 80h 40h 10h 42h 40h 44h 40h 4ah 08h * all other registers are set to default/normal settings. for pal cvbs output on dac a, the sam e settings are used except that subaddress 40h is changed to 11h. the following register settings are used to generate an sd ntsc black bar pattern output on dac a. register subaddress setting 00h 80h 02h 04h 40h 10h 42h 40h 44h 40h 4ah 08h * all other registers are set to default/normal settings. for pal black bar pattern output on dac a, the same settings are used except that subaddress = 40h and register setting = 11h. the following register settings are used to generate a 525p hatch pattern on dac d. register subaddress setting 00h 80h 01h 10h 10h 40h 11h 05h 16h a0h 17h 80h 18h 80h * all other registers are set to default/normal settings. for 625p hatch pattern on dac d, the same register settings are used except that subaddress = 10h and register setting = 50h. for a 525p black bar pattern output on dac d, the same settings are used as for a 525p hatch pattern except that subaddress = 02h and register setting = 24h. for 625p black bar pattern output on dac d, the same settings are used as for a 625p hatch pattern except that subaddress = 02h and register setting = 24h; and subaddress = 10h and register setting = 50h.
rev. 0 e66e ADV7314 appendix 5?sd timing modes [subaddress 4ah] mode 0 (ccir-656)?slave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7314 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pat- tern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. s_vsync s_hsync s_blank b y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data ( hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc /pal m system pal system y (525 lines/60hz) (625 lines/50hz) figure 77. sd slave mode 0
rev. 0 ADV7314 e67e mode 0 (ccir-656)?master option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7314 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on s_hsync v s_blank s_vsync 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f h v f figure 78. sd master mode 0 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 h v f h v f figure 79. sd master mode 0 (pal)
rev. 0 e68e ADV7314 mode 1?slave option (timing register 0 tr0 = x x x x x 0 1 0) in this mode, the ADV7314 accepts horizontal sync and odd/even field signals. a transition of the field input when hsync t blank w blank av ccr hsync hsync blank s_blank el s_vsync analog video h v f figure 80. sd master mode 0, data transitions 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field field h sync b lank field hsync blank ssntsc
rev. 0 ADV7314 e69e mode 1?master option (timing register 0 tr0 = x x x x x 0 1 1) in this mode, the ADV7314 can generate horizontal sync and odd/ even field signals. a transition of the field input when hsync t blank w blank av ccr p hsync s_hsync blank s_blank el s_vsync 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 h sync b lank field h sync b lank sspal field pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y h sync b lank stets
rev. 0 e70e ADV7314 mode 2?slave option (timing register 0 tr0 = x x x x x 1 0 0) in this mode, the ADV7314 accepts horizontal and vertical sync signals. a coincident low transition of both hsync vsync a vsync hsync t blank w blank av ccr hsync s_ hsync blank s_blank vsync s_vsync 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h sync b lank vsync h sync b lank vsync ssntsc 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field h sync b lank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 h sync b lank vsync sspal
rev. 0 ADV7314 e71e pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y h sync vsync b lank pixel data figure 86. sd timing mode 2 even-to-odd field transition master/slave pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 h sync vsync b lank pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb figure 87. sd timing mode 2 odd-to-even field transition master/slave mode 2?master option (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the ADV7314 can generate horizontal and vertical sync signals. a coincident low transition of both hsync vsync a vsync hsync t blank w blank av ccr hsync s_hsync blank s_blank vsync s_vsync
rev. 0 e72e ADV7314 mode 3?master/slave option (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7314 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync t blank w blank av ccr hsync s_ hsync blank s_blank vsync s_vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field h sync b lank field h sync b lank field figure 88. sd timing mode 3 (ntsc) 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field h sync b lank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field h sync b lank field display 320 figure 89. sd timing mode 3 (pal)
rev. 0 ADV7314 e73e appendix 6?hd timing 1124 1125 12 3 4 5 67 8 20 21 22 560 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 field 1 field 2 vertical blanking interval vertical blanking interval p _vsync p _hsync p _vsync p _hsync display display figure 90. 1080i hsync vsync t
rev. 0 e74e ADV7314 appendix 7?video output levels hd yprpb output levels input code 940 64 eia-770.2, standard for y output voltage 300mv 700mv 700mv 960 64 eia-770.2, standard for pr/pb output voltage 512 figure 91. eia 770.2 standard output signals (525p/625p) 782mv 714mv 286mv 700mv input code 940 64 eia-770.1, standard for y output voltage 960 64 eia-770.1, standard for pr/pb output voltage 512 figure 92. eia 770.1 standard output signals (525p/625p) 300mv input code 940 64 eia-770.3, standard for y output voltage 700mv 700mv 600mv 960 64 eia-770.3, standard for pr/pb output voltage 512 figure 93. eia 770.3 standard output signals (1080i, 720p) 300mv 300mv 700mv 700mv input code 1023 64 y?output levels for full input selection output voltage 1023 64 pr/pb?output levels for full input selection output voltage input code figure 94. output levels for full input selection
rev. 0 ADV7314 e75e 300mv 300mv 300mv 700mv 700mv 550mv 550mv 700mv 550mv figure 95. hd rgb output levels 300mv 0mv 300mv 0mv 300mv 0mv 700mv 550mv 700mv 550mv 700mv 550mv figure 96. hd rgb output levels?rgb sync enabled 300mv 300mv 300mv 700mv 700mv 550mv 550mv 700mv 550mv figure 97. sd rgb output levels?rgb sync disabled 300mv 0mv 300mv 0mv 300mv 0mv 700mv 550mv 700mv 550mv 700mv 550mv figure 98. sd rgb output levels?rgb sync enabled rgb output levels
rev. 0 e76e ADV7314 yprpb output levels 160mv 220mv white yellow cyan green magenta red blue black 60mv 110mv 280mv 332mv figure 99. u levels?ntsc 160mv 220mv white yellow cyan green magenta red blue black 60mv 110mv 280mv 332mv figure 100. u levels?pal 1000mv white yellow cyan green magenta red blue black 1260mv 140mv 200mv 2150mv 900mv figure 101. u levels?ntsc 1000mv white yellow cyan green magenta red blue black 1260mv 140mv 200mv 2150mv 900mv figure 102. u levels?pal white yellow cyan green magenta red blue black 300mv figure 103. y levels?ntsc white yellow cyan green magenta red blue black 300mv figure 104. y levels?pal
rev. 0 ADV7314 e77e 0.5 volts 0 apl = 44.5% 525 line ntsc slow clamp to 0.00v at 6.72 s microseconds precision mode off synchronous sync = a frames selected 1 2 10 20 f1 l76 30 40 50 60 ire:flt 100 50 0 ?50 0 figure 105. ntsc color bars 75% volts 0 noise reduction: 15.05db apl needs sync-source! 525 line ntsc no filtering slow clamp to 0.00 at 6.72 s microseconds precision mode off synchronous sync = b frames selected 1 2 10 20 f1 l76 30 40 50 60 ire:flt 50 ?50 0 0.4 0.2 0 ?0.2 ?0.4 figure 106. ntsc chroma
rev. 0 e78e ADV7314 volts noise reduction: 15.05db apl = 44.3% 525 line ntsc no filtering slow clamp to 0.00 at 6.72 s microseconds precision mode off synchronous sync = source frames selected 1 2 10 20 f2 l238 30 40 50 60 ire:flt 50 0 0 0.4 0.2 0.6 0 ?0.2 figure 107. ntsc luma volts noise reduction: 0.00db apl = 39.1% 625 line ntsc no filtering slow clamp to 0.00 at 6.72 s microseconds precision mode off synchronous sound-in-sync off frames selected 1 2 3 4 10 020 l608 30 40 50 60 0.4 0.2 0.6 0 ?0.2 figure 108. pal color bars 75%
rev. 0 ADV7314 e79e volts apl needs sync source! 625 line pal no filtering slow clamp to 0.00 at 6.72 s microseconds no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 10 20 l575 30 40 50 60 0 0.5 ?0.5 figure 109. pal chroma volts apl needs sync source! 625 line pal no filtering slow clamp to 0.00 at 6.72 s microseconds no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 10 020 l575 30 40 50 60 70 0 0.5 figure 110. pal luma
rev. 0 e80e ADV7314 f v h * f f 272t 4t * 1 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h * c b c r c r y y fvh * = fvh and parity bits sav/eav: line 1?562: f = 0 sav/eav: line 563?1125: f = 1 sav/eav: line 1?20; 561?583; 1124?1125: v = 1 sav/eav: line 21?560; 584?1123: v = 0 for a field rate of 30hz: 40 samples for a field rate of 25hz: 480 samples input pixels analog waveform sample number smpte 274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum figure 111. eav/sav input data timing diagram?smpte 274m y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 fvh * = fvh and parity bits sav: line 43?525 = 200h sav: line 1?42 = 2ac eav: line 43?525 = 274h eav: line 1?42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h * smpte 293m input pixels analog waveform sample number f f f f f v h * figure 112. eav/sav input data timing diagram?smpte 293m appendix 8?video standards
rev. 0 ADV7314 e81e vertical blank 522 523 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 44 active video active video figure 113. smpte 293m (525p) vertical blank active video active video 622 623 624 625 1 2 5 6 7 8 9 12 13 10 11 43 44 45 4 figure 114. itu-r bt.1358 (625p) 747 748 749 750 1 2 5 6 7 8 26 27 25 744 745 4 display 3 vertical blanking interval figure 115. smpte 296m (720p) display 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 vertical blanking interval vertical blanking interval figure 116. smpte 274m (1080i)
rev. 0 e82e ADV7314 outline dimensions 64-lead low profile quad flat package [lqfp] (st-64) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc sq 1.60 max seating plane 0.75 0.60 0.45 view a 12.00 bsc sq 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bcd
e83e
c03749e0e8/03(0) e84e

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